1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same. In particular, the present invention relates to a semiconductor device including a wiring board and a semiconductor element that is mounted on the wiring board, and to a method for manufacturing the same.
2. Related Background Art
Techniques for connecting a semiconductor element to conductors of a wiring board can be divided broadly into (1) wire bonding (WB) method (see JP H4-286134A, for example), (2) flip chip bonding (FC) method (see JP 2000-36504A, for example), (3) TAB (tape automated bonding) method (see JP H8-88245A, for example), and the like. Hereinafter, these methods will be described briefly.
First, the WB method will be described with reference to FIGS. 17A, 17B, and 18. FIG. 17A is a plan view for explaining a state in which a semiconductor chip and a lead frame are connected to each other by bonding wires, and FIG. 17B is a cross-sectional view taken along the line A—A in FIG. 17A. FIG. 18 is a cross-sectional view of a semiconductor device for which the WB method is employed.
As shown in FIGS. 17A and 17B, in the WB method, the semiconductor chip 501 is first die-bonded to a die pad 504 of the lead frame. Then, wire bonding pads 502 of the semiconductor chip 501 are connected to inner lead portions of external terminals 505 of the lead frame via the bonding wires 503. Subsequently, as shown in FIG. 18, a region including the semiconductor chip 501 and the inner lead portions of the external terminals 505 is sealed with a sealing resin 506, and thus a resin-sealed product (semiconductor device) 500 is obtained.
Next, the FC method will be described with reference to FIG. 19. FIG. 19 shows a cross-sectional configuration of a semiconductor device 600 for which the FC method is employed. In the FC method, wiring layers 602 of a substrate 601 (wiring board) are connected to electrodes 604 of a semiconductor chip 605 via bumps 603. A gap between the substrate 601 and the semiconductor chip 605 is sealed with a sealing resin 607, and the wiring layers 602, the bumps 603, and the electrodes 604 are embedded in the sealing resin 607. In FIG. 19, numeral 606 indicates a sensitive area in which a transistor, for example, is formed.
Next, a semiconductor device for which the TAB method is employed will be described with reference to FIGS. 20 to 23. FIGS. 20 and 22 show a cross-sectional configuration of the semiconductor device 700 for which the TAB method is employed, and FIGS. 21 and 23 show a state in which the semiconductor device 700 is mounted on a mount board 709.
The semiconductor device 700 shown in FIGS. 20 and 22 includes a base film 702 and a semiconductor IC chip 701. The semiconductor IC chip 701 is disposed in a device hole that is formed in the base film 702. Copper foil conductors 703 are formed on one face of the base film 702. Electrodes 701a of the semiconductor IC chip 701 are connected to inner tip portions (inner leads 703a) of the copper foil conductors 703. At portions of the copper foil conductor 703 that are located on the outer side relative to the inner lead 703a, there are provided lands 703b for external connection. Solder bumps 706 are connected to the lands 703b. Through holes 702a are formed in the base film 702, and a pore 703c is formed at the center of each land 703b. A cover resist 704 is formed on the base film 702. The device hole is filled up with a sealing resin 705 for protecting the semiconductor IC chip 701.
In this semiconductor device 700, the solder bumps 706 serve as outer leads. As shown in FIGS. 21 and 23, the solder bumps 706 are placed on pads 709a on the mount board 709, and the semiconductor device 700 is mounted on the mount board 709 using a mass reflow process.
However, in the semiconductor device 500 for which the WB method is employed, the wire bonding pads 502 and the external terminals 505 are connected to each other one by one by the bonding wires 503. Thus, there is a problem in that as the number of wire bonding pads 502 or external terminals 505 increases, the time and effort required for the operation increase and productivity decreases (see FIGS. 17A and 17B). As shown in FIG. 18, the semiconductor device 500 for which the WB method is employed has a structure in which a portion of each bonding wire 503 is positioned below the lower surface of the semiconductor chip 501, in this drawing, and the semiconductor chip 501 and the bonding wires 503 are sealed with the sealing resin 506. Therefore, there is a significant limitation in reducing the thickness of the semiconductor device 500. Moreover, the spacing between the adjacent wire bonding pads 502 is defined by the spacing between the adjacent external terminals 505. The external terminals 505 are soldered to the substrate. Thus, in the present circumstances, the spacing between the external terminals is about 0.4 mm so that problems such as short-circuiting between the external terminals can be prevented. Even if the spacing between the wire bonding pads 502 of the semiconductor chip can be reduced, it is difficult to reduce the spacing between the external terminals 505 to less than 0.4 mm. This fact has been a hindrance to reducing the size of the semiconductor device.
The semiconductor device 600 (see FIG. 19) for which the FC method is employed has the following problems. In the semiconductor device for which the FC method is employed, the spacing between the adjacent electrodes 604 is smaller than the spacing between the external terminals 505 (see FIG. 17). Therefore, alignment of the semiconductor chip 605 and the substrate 601 needs to be performed with very high accuracy.
Moreover, there also is a problem in that the substrate 601 tends to be expensive. The reason for this is that in the semiconductor device for which the FC method is employed, the substrate 601 is required to have the wiring layer 602 that includes fine conductors corresponding to the electrodes 604 of the semiconductor chip 605. Another reason is that when there is a large number of electrodes 604, the substrate 601 (wiring board) is required to have a multilayer structure, which leads to an increase in the cost.
Moreover, the semiconductor device 600 for which the FC method is employed has a structure in which the semiconductor chip 605 is connected to the wiring board 601 via the bumps 603, so that it is necessary to match the coefficient of linear thermal expansion of the semiconductor chip 605 with the coefficient of linear thermal expansion of the substrate 601 as closely as possible. The reason for this is that when there is a great difference between the coefficient of linear thermal expansion of the semiconductor chip 605 and the coefficient of linear thermal expansion of the substrate 601, a stress is applied to, for example, the bumps 603, and thus the electric connection between the semiconductor chip 605 and the wiring board 601 may be damaged. Therefore, it is necessary to match the coefficients of linear thermal expansion of these two components, and thus there is a severe limitation on the material selection.
Furthermore, in the semiconductor device 600 for which the FC method is employed, after connecting the semiconductor chip 605 to the substrate 601 via the bumps 603, the gap between the semiconductor chip 605 and the substrate 601 is filled up with a resin (underfill agent) 607, and this step increases the cost and also the number of steps, so that productivity decreases. Moreover, there also is a problem in that the heat dissipation of the semiconductor chip in the semiconductor device 600 for which the FC method is employed is lower than that in the semiconductor device for which the WB method is employed. In the semiconductor device for which the WB method is employed, one face of the body portion of the semiconductor chip is secured to the die pad having high heat conductivity via a thin bonding-material layer that is constituted by resin, solder, and the like, so that the heat dissipation of the semiconductor chip is relatively high. On the other hand, in the semiconductor device for which the FC method is employed, the semiconductor chip 605 is connected to the substrate 601 via the bumps 603, so that the distance between a face of the body portion of the semiconductor chip 605 that is in opposition to the substrate 601 and a face on the semiconductor element 605 side of the substrate 601 is larger than in the semiconductor device for which the WB method is employed, and thus, the heat dissipation of the semiconductor chip is low. Moreover, in the manufacturing process of the semiconductor device 600 for which the FC method is employed, it is necessary to form the bumps 603, which takes time and effort.
The semiconductor device 700 for which the TAB method is employed has the following problems. In the manufacturing process of the semiconductor device 700 for which the TAB method is employed, an inner lead bonding (ILB) step in which the electrodes 701a of the semiconductor IC chip 701 are connected to the inner leads 703a and an outer lead bonding (OLB) step in which the solder bumps 706 are formed at the lands 703b are performed using completely different methods, and thus these steps take time and effort. Moreover, it is necessary to seal the semiconductor IC chip 701 that is disposed in the device hole with the sealing resin 705. This step also takes time and effort, so that the productivity of the semiconductor device 700 for which the TAB method is employed is low.
The present invention provides a semiconductor device for which the disadvantages of the semiconductor devices for which the WB method, the FC method, or the TAB method is employed has been reduced. The present invention provides a semiconductor device having high productivity, for example.